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FPGA
2010
ACM
243views FPGA» more  FPGA 2010»
16 years 1 months ago
Bit-level optimization for high-level synthesis and FPGA-based acceleration
d hardware design from behavior-level abstraction has drawn wide interest in FPGA-based acceleration and configurable computing research field. However, for many high-level progra...
Jiyu Zhang, Zhiru Zhang, Sheng Zhou, Mingxing Tan,...
AHS
2007
IEEE
252views Hardware» more  AHS 2007»
15 years 11 months ago
A Hybrid Engine for the Placement of Domain-Specific Reconfigurable Arrays
Rapid-prototyping of commercial devices and the demanding requirements for flexible hardware in mobile applications have driven the raise of reconfigurable hardware. The adaptatio...
Wing On Fung, Tughrul Arslan, Sami Khawam
FCCM
2007
IEEE
100views VLSI» more  FCCM 2007»
15 years 10 months ago
A Library and Platform for FPGA Bitstream Manipulation
— Since 1998, no commercially available FPGA has been accompanied by public documentation of its native machine code (or bitstream) format. Consequently, research in reconfigura...
Adam Megacz
CHES
2007
Springer
126views Cryptology» more  CHES 2007»
15 years 10 months ago
How to Maximize the Potential of FPGA Resources for Modular Exponentiation
This paper describes a modular exponentiation processing method and circuit architecture that can exhibit the maximum performance of FPGA resources. The modular exponentiation arch...
Daisuke Suzuki
FCCM
2006
IEEE
144views VLSI» more  FCCM 2006»
15 years 10 months ago
Combining Instruction Coding and Scheduling to Optimize Energy in System-on-FPGA
In this paper, we investigate a combination of two techniques — instruction coding and instruction re-ordering — for optimizing energy in embedded processor control. We presen...
Robert G. Dimond, Oskar Mencer, Wayne Luk