897 search results - page 147 / 180 » System-Level Design for FPGAs |
109
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GLOBECOM
2006
IEEE
15 years 10 months ago
2006
IEEE
— We present a field programmable gate array (FPGA) implementation of a turbo-like decoder for a serially concatenated pulse-position modulation (SCPPM) code. NASA developed thi...
134
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ISCAS
2005
IEEE
15 years 10 months ago
2005
IEEE
Abstract — FPGAs offer excellent platform for System-onChips consisting of Intellectual Property (IP) blocks. The problem is that IP blocks and their interconnections are often F...
128
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ITCC
2005
IEEE
15 years 10 months ago
2005
IEEE
Abstract— Masking is a general method used to thwart Differential Power Analysis, in which all the intermediate data inside an implementation are XORed with random Boolean values...
170
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FPL
2005
Springer
15 years 10 months ago
2005
Springer
With the onset of Gigabit networks, current generation networking components will soon be insufficient for numerous reasons: most notably because existing methods cannot support h...
147
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FPL
2005
Springer
15 years 10 months ago
2005
Springer
A module generator called Mullet for producing near-optimal parallel multipliers in a technology independent manner is presented. Using this tool, a large number of candidate desi...