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MSE
1999
IEEE
118views Hardware» more  MSE 1999»
15 years 8 months ago
Training IP Creators and Integrators
Intellectual property IP blocks are being created for reuse and marketed as a means of reducing the development time of complex designs. This in turn leads to a reduction in time ...
Donald W. Bouldin, Senthil Natarajan, Benjamin A. ...
FCCM
1998
IEEE
111views VLSI» more  FCCM 1998»
15 years 8 months ago
A Stream-Based Configurable Computing Radio Testbed
Software radios have emerged as important tools in the development of new signal processing algorithms, networking protocols, and propagation experiments in wireless environments....
Steven Swanchara, Scott J. Harper, Peter M. Athana...
FPGA
1997
ACM
145views FPGA» more  FPGA 1997»
15 years 8 months ago
Generation of Synthetic Sequential Benchmark Circuits
Programmable logic architectures increase in capacity before commercial circuits are designed for them, yielding a distinct problem for FPGA vendors: how to test and evaluate the ...
Michael D. Hutton, Jonathan Rose, Derek G. Corneil
FPGA
2006
ACM
111views FPGA» more  FPGA 2006»
15 years 8 months ago
FPGA clock network architecture: flexibility vs. area and power
This paper examines the tradeoffs between flexibility, area, and power dissipation of programmable clock networks for FieldProgrammable Gate Arrays (FPGA's). The paper begins...
Julien Lamoureux, Steven J. E. Wilton
ASPDAC
2001
ACM
120views Hardware» more  ASPDAC 2001»
15 years 8 months ago
Virtual Java/FPGA interface for networked reconfiguration
Abstract- Avirtual interfacebetweenJava andFPGA for networked reconfigurationis presented. ThroughtheJavaflFPGAinterface,Java applicationscan exploithardwareaccelerators with FPGAs...
Yajun Ha, Geert Vanmeerbeeck, Patrick Schaumont, S...