897 search results - page 170 / 180 » System-Level Design for FPGAs |
123
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DATE
2006
IEEE
15 years 10 months ago
2006
IEEE
We present a de-layered protocol engine for termination of 40Gbps TCP connections using a reconfigurable FPGA silicon platform. This protocol engine is designed for a planned att...
118
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ISCAS
2006
IEEE
15 years 10 months ago
2006
IEEE
In this paper a 173-bit type II ONB ECC processor Section II introduces the mathematical backgrounds for for inductive RFID applications is described. Compared with curve operation...
112
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GLVLSI
2005
IEEE
15 years 10 months ago
2005
IEEE
The ever-increasing number of transistors on a chip has resulted in very large scale integration (VLSI) systems whose performance and manufacturing costs are driven by on-chip wir...
96
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ISCAS
2005
IEEE
15 years 10 months ago
2005
IEEE
Multiprocessor system-on-chip (MP-SoC) platforms are emerging as an important trend of SoC design. Scaleable communication-centric interconnect fabrics such as networks-onchip (No...
125
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DATE
2010
IEEE
15 years 9 months ago
2010
IEEE
—Recent developments have shown the possibility of leveraging silicon nanophotonic technologies for chip-scale interconnection fabrics that deliver high bandwidth and power effi...