897 search results - page 22 / 180 » System-Level Design for FPGAs |
107
Voted
3DIC
2009
IEEE
15 years 7 months ago
2009
IEEE
- This paper describes a new architectural paradigm for fully connected, single-hop system level interconnection networks. The architecture is scalable enough to meet the needs of ...
105
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VLSID
2007
IEEE
15 years 6 months ago
2007
IEEE
In this paper we demonstrate the impact of the floorplan on the temperature-dependent leakage power of a System on Chip (SoC). We propose a novel system level temperature aware a...
97
Voted
DATE
2003
IEEE
15 years 5 months ago
2003
IEEE
Today’s mobile communication systems use sophisticated signal processing to achieve high transmission rates. Therefore a high complexity in the digital system part as well as ve...
79
Voted
CODES
2001
IEEE
15 years 4 months ago
2001
IEEE
This paper presents a practical approach to communication synthesis for hardware/software system specified as tasks communicating through lossless blocking channels. It relies on ...
84
Voted
ICCAD
2001
IEEE
15 years 9 months ago
2001
IEEE
In this work, we provide a technique for efficiently exploring the configuration space of a parameterized system-on-a-chip (SOC) architecture to find all Pareto-optimal configurat...