897 search results - page 27 / 180 » System-Level Design for FPGAs |
TRIDENTCOM
2006
IEEE
15 years 6 months ago
2006
IEEE
— Telecommunication networks have rapidly added staggering amounts of capacity to their long haul networks at low costs per bit using DWDM technologies. Concurrently, there has b...
99
Voted
FPL
2009
Springer
15 years 3 months ago
2009
Springer
In this paper we discuss how various design components perform in both FPGAs and standard cell based ASICs. We also investigate how various common FPGA optimizations will effect t...
73
Voted
ASPDAC
2008
ACM
15 years 2 months ago
2008
ACM
104
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FDL
2003
IEEE
15 years 5 months ago
2003
IEEE
The paper presents a methodology to integrate information on power consumption in a high level functional description of a System-on-chip. The power dissipated during the executio...
87
Voted
FPGA
1998
ACM
15 years 4 months ago
1998
ACM
In designing FPGAs, it is important to achieve a good balance between the number of logic blocks, such as Look-Up Tables (LUTs), and wiring resources. It is dicult to nd an optim...