897 search results - page 34 / 180 » System-Level Design for FPGAs |
93
Voted
DATE
2005
IEEE
15 years 6 months ago
2005
IEEE
Triple Modular Redundancy (TMR) is a suitable fault tolerant technique for SRAM-based FPGA. However, one of the main challenges in achieving 100% robustness in designs protected b...
119
Voted
ARC
2007
Springer
15 years 6 months ago
2007
Springer
Abstract. The novel design of high-speed and low-energy FPGA routing architecture consisting of appropriate wire segments and multiple Switch Boxes is introduced. For that purpose,...
113
Voted
JUCS
2007
15 years 15 days ago
2007
: The development of processors with full custom technology has some disadvantages, such as the time used to design the processors and the cost of the implementation. In this artic...
ICCD
2008
IEEE
15 years 9 months ago
2008
IEEE