897 search results - page 38 / 180 » System-Level Design for FPGAs |
88
Voted
DAC
2004
ACM
16 years 1 months ago
2004
ACM
We present novel and efficient methods for on-line testing in FPGAs. The testing approach uses a ROving TEster (ROTE), which has provable diagnosabilities and is also faster than ...
54
Voted
DAC
2004
ACM
16 years 1 months ago
2004
ACM
110
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ARC
2010
Springer
15 years 25 days ago
2010
Springer
Using FPGAs to accelerate High Performance Computing (HPC) applications is attractive, but has a huge associated cost: the time spent, not for developing efficient FPGA code but fo...
99
Voted
FPGA
2003
ACM
15 years 5 months ago
2003
ACM
This paper proposes a new high-level technique for designing fault tolerant systems in SRAM-based FPGAs, without modifications in the FPGA architecture. Traditionally, TMR has bee...
105
Voted
SAMOS
2005
Springer
15 years 6 months ago
2005
Springer
This paper presents a new tool for the automatic generation of highly parallelized Finite Impulse Response (FIR) filters. In this approach we follow our PARO design methodology. P...