Sciweavers

897 search results - page 39 / 180
» System-Level Design for FPGAs
Sort
View
FPGA
2004
ACM
121views FPGA» more  FPGA 2004»
15 years 6 months ago
Highly pipelined asynchronous FPGAs
We present the design of a high-performance, highly pipelined asynchronous FPGA. We describe a very fine-grain pipelined logic block and routing interconnect architecture, and sh...
John Teifel, Rajit Manohar
95
Voted
DATE
2002
IEEE
83views Hardware» more  DATE 2002»
15 years 5 months ago
Reconfigurable SoC - What Will it Look Like?
The argument against ASIC SoCs is that they have always taken too long and cost too much to design. As new process technologies come on line, the issue of inflexible, unyielding d...
J. Bryan Lewis, Ivo Bolsens, Rudy Lauwereins, Chri...
118
Voted
FPGA
2005
ACM
195views FPGA» more  FPGA 2005»
15 years 6 months ago
Sparse Matrix-Vector multiplication on FPGAs
Floating-point Sparse Matrix-Vector Multiplication (SpMXV) is a key computational kernel in scientific and engineering applications. The poor data locality of sparse matrices sig...
Ling Zhuo, Viktor K. Prasanna
94
Voted
FPL
2001
Springer
92views Hardware» more  FPL 2001»
15 years 5 months ago
Secure Configuration of Field Programmable Gate Arrays
Although SRAM programmed Field Programmable Gate Arrays (FPGA's) have come to dominate the industry due to their density and performance advantages over non-volatile technolog...
Tom Kean
96
Voted
KES
2006
Springer
15 years 17 days ago
Implementation of a FIR Filter on a Partial Reconfigurable Platform
This paper presents our implemented, synthesized and tested on demand and partial reconfiguration approaches for FIR filters using Xilinx Virtex FPGAs. Our scope is to implement a ...
Hanho Lee, Chang-Seok Choi