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» System-Level Design for FPGAs
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FPGA
2010
ACM
250views FPGA» more  FPGA 2010»
16 years 20 days ago
Variation-aware placement for FPGAs with multi-cycle statistical timing analysis
Deep submicron processes have allowed FPGAs to grow in complexity and speed. However, such technology scaling has caused FPGAs to become more susceptible to the effects of process...
Gregory Lucas, Chen Dong, Deming Chen
ERSA
2004
129views Hardware» more  ERSA 2004»
15 years 5 months ago
A Methodology for Energy Efficient Application Synthesis Using Platform FPGAs
Platform FPGAs incorporate many different components, such as processor core(s), reconfigurable logic, memory, etc., onto a single chip. When an application is synthesized on platf...
Jingzhao Ou, Viktor K. Prasanna
SLIP
2006
ACM
15 years 9 months ago
The routability of multiprocessor network topologies in FPGAs
A fundamental difference between ASICs and FPGAs is that wires in ASICs are designed such that it matches the requirements of a particular design. Wire parameters such as: length...
Manuel Saldaña, Lesley Shannon, Paul Chow
FPGA
2004
ACM
136views FPGA» more  FPGA 2004»
15 years 9 months ago
Active leakage power optimization for FPGAs
We consider active leakage power dissipation in FPGAs and present a “no cost” approach for active leakage reduction. It is well-known that the leakage power consumed by a digi...
Jason Helge Anderson, Farid N. Najm, Tim Tuan
DATE
2010
IEEE
180views Hardware» more  DATE 2010»
15 years 9 months ago
Reliability- and process variation-aware placement for FPGAs
Abstract—Negative bias temperature instability (NBTI) significantly affects nanoscale integrated circuit performance and reliability. The degradation in threshold voltage (Vth) d...
Assem A. M. Bsoul, Naraig Manjikian, Li Shang