897 search results - page 51 / 180 » System-Level Design for FPGAs |
147
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FPGA
2003
ACM
15 years 9 months ago
2003
ACM
In this paper, we present the first exact algorithm to solve the constrained I/O placement problem for FPGAs that support multiple I/O standards. We derive a compact integer line...
166
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FPGA
2001
ACM
15 years 8 months ago
2001
ACM
Discrete wavelet transformations (DWT) followed by embedded zerotree encoding is a very efficient technique for image compression [2, 5, 4]. However, the algorithms proposed in l...
VLSID
2007
IEEE
16 years 4 months ago
2007
IEEE
State-of-the-art FPGA architectures have millions of gates in CLBs, Block RAMs, and Multiplier blocks which can host fairly large designs. While their physical design calls for oor...
103
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ISCAS
2003
IEEE
15 years 9 months ago
2003
IEEE
This paper presents a new family of architectures for multi-cycle area-efficient evaluation of elementary and composite functions, and an exploration of the design tradeoffs for i...
131
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IPPS
2002
IEEE
15 years 9 months ago
2002
IEEE
Reconfigurable computing based on partial reconfiguration of field programmable gate arrays (FPGAs) is yet to move to the mainstream of computing. Hardware devices that support su...