897 search results - page 57 / 180 » System-Level Design for FPGAs |
136
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FPGA
2007
ACM
15 years 10 months ago
2007
ACM
This paper describes a technique that reduces dynamic power in FPGAs by reducing the number of glitches in the global routing resources. The technique involves adding programmable...
118
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DATE
2003
IEEE
15 years 9 months ago
2003
IEEE
In today’s deep-submicron designs, the interconnect delays contribute an increasing part to the overall performance of an implementation. Particularly when targeting field prog...
119
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FCCM
2004
IEEE
15 years 8 months ago
2004
IEEE
This paper presents ADB, an Alternate Wire Database, suitable for routing, tracing, and browsing in Xilinx Virtex, Virtex-E, Virtex-II, and Virtex-II Pro FPGAs. While mainstream d...
119
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TACO
2008
15 years 4 months ago
2008
r acceptance of FPGAs as a computing device requires a higher level of programming abstraction. ROCCC is an optimizing C to HDL compiler. We describe the code generation approach i...
142
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FPGA
2010
ACM
16 years 1 months ago
2010
ACM
Placement based on simulated annealing is in dominant use in the FPGA community due to its superior quality of result (QoR). However, given the progression of FPGA device capacity...