Sciweavers

897 search results - page 59 / 180
» System-Level Design for FPGAs
Sort
View
CHES
2003
Springer
104views Cryptology» more  CHES 2003»
15 years 9 months ago
Power-Analysis Attacks on an FPGA - First Experimental Results
Field Programmable Gate Arrays (FPGAs) are becoming increasingly popular, especially for rapid prototyping. For implementations of cryptographic algorithms, not only the speed and ...
Siddika Berna Örs, Elisabeth Oswald, Bart Pre...
ECOOP
2008
Springer
15 years 6 months ago
Liquid Metal: Object-Oriented Programming Across the Hardware/Software Boundary
Abstract. The paradigm shift in processor design from monolithic processors to multicore has renewed interest in programming models that facilitate parallelism. While multicores ar...
Shan Shan Huang, Amir Hormati, David F. Bacon, Rod...
FPL
2007
Springer
140views Hardware» more  FPL 2007»
15 years 10 months ago
An area-efficient alternative to adaptive median filtering in FPGAs
This paper presents a new approach to the FPGA implementation of image filters which are utilized to remove the saltand-pepper noise of high intensity (up to 70% of corrupted pix...
Zdenek Vasícek, Lukás Sekanina
FPL
2004
Springer
147views Hardware» more  FPL 2004»
15 years 9 months ago
Partial and Dynamically Reconfiguration of Xilinx Virtex-II FPGAs
Current trends show that partial and dynamic reconfiguration can be used in adaptive systems. These systems are able to adapt themselves to the demand of their environment during r...
Brandon Blodget, Christophe Bobda, Michael Hü...
DFT
2007
IEEE
152views VLSI» more  DFT 2007»
15 years 8 months ago
TMR and Partial Dynamic Reconfiguration to mitigate SEU faults in FPGAs
This paper presents the adoption of the Triple Modular Redundancy coupled with the Partial Dynamic Reconfiguration of Field Programmable Gate Arrays to mitigate the effects of Sof...
Cristiana Bolchini, Antonio Miele, Marco D. Santam...