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» System-Level Design for FPGAs
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DAC
2012
ACM
13 years 6 months ago
Chisel: constructing hardware in a Scala embedded language
In this paper we introduce Chisel, a new hardware construction language that supports advanced hardware design using highly parameterized generators and layered domain-specific h...
Jonathan Bachrach, Huy Vo, Brian Richards, Yunsup ...
AFRICACRYPT
2008
Springer
15 years 10 months ago
Implementation of the AES-128 on Virtex-5 FPGAs
Abstract. This paper presents an updated implementation of the Advanced Encryption Standard (AES) on the recent Xilinx Virtex-5 FPGAs. We show how a modified slice structure in th...
Philippe Bulens, François-Xavier Standaert,...
FPGA
2001
ACM
137views FPGA» more  FPGA 2001»
15 years 8 months ago
A crosstalk-aware timing-driven router for FPGAs
As integrated circuits are migrated to more advanced technologies, it has become clear that crosstalk is an important physical phenomenon that must be taken into account. Crosstal...
Steven J. E. Wilton
FPGA
2006
ACM
92views FPGA» more  FPGA 2006»
15 years 8 months ago
Embedded floating-point units in FPGAs
Due to their generic and highly programmable nature, FPGAs provide the ability to implement a wide range of applications. However, it is this nonspecific nature that has limited t...
Michael J. Beauchamp, Scott Hauck, Keith D. Underw...
CC
2008
Springer
240views System Software» more  CC 2008»
15 years 6 months ago
Hardware JIT Compilation for Off-the-Shelf Dynamically Reconfigurable FPGAs
JIT compilation is a model of execution which translates at run time critical parts of the program to a low level representation. Typically a JIT compiler produces machine code fro...
Etienne Bergeron, Marc Feeley, Jean-Pierre David