897 search results - page 63 / 180 » System-Level Design for FPGAs |
110
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VLSID
2009
IEEE
16 years 4 months ago
2009
IEEE
Partial Reconfiguration on heterogeneous Field Programmable Gate Arrays (FPGA) with millions of gates yields better utilization of resources by swapping in and out the active modu...
141
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FCCM
2009
IEEE
15 years 11 months ago
2009
IEEE
—We present a parameterized stereo vision core suitable for a wide range of FPGA targets and stereo vision applications. By enabling easy tuning of algorithm parameters, our syst...
133
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ASAP
2008
IEEE
15 years 10 months ago
2008
IEEE
Reconfigurable circuits now have a capacity that allows them to be used as floating-point accelerators. They offer massive parallelism, but also the opportunity to design optimi...
115
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FPL
2005
Springer
15 years 9 months ago
2005
Springer
This work explores the effect of adding a timing driven functional decomposition step to the traditional field programmable gate array (FPGA) CAD flow. Once placement has comple...
122
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FPL
2000
Springer
15 years 7 months ago
2000
Springer
Abstract. In this paper we outline a procedure to determine appropriate partitioning of programmable logic and interconnect area to minimize overall device area across a broad rang...