897 search results - page 75 / 180 » System-Level Design for FPGAs |
138
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IOLTS
2007
IEEE
15 years 10 months ago
2007
IEEE
In this paper we present an efficient design technique for implementing the Elliptic Curve Cryptographic (ECC) Scheme in FPGAs. Our technique is based on a novel and efficient i...
129
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IPPS
2005
IEEE
15 years 10 months ago
2005
IEEE
Soft-core processors exploit the flexibility of Field Programmable Gate Arrays (FPGAs) to allow a system designer to customize the processor to the needs of a target application....
149
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IPPS
2006
IEEE
15 years 10 months ago
2006
IEEE
The increasing demand for FPGAs and reconfigurable hardware targeting high performance low power applications has lead to an increasing requirement for new high performance reconf...
143
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FPGA
2008
ACM
15 years 6 months ago
2008
ACM
Logical effort (LE) is a linear technique for modelling the delay of a circuit in a technology independent manner. It offers the potential to simplify delay models for FPGAs and g...
157
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FPGA
2005
ACM
15 years 10 months ago
2005
ACM
Creating a new FPGA is a challenging undertaking because of the significant effort that must be spent on circuit design, layout and verification. It currently takes approximately ...