Sciweavers

897 search results - page 79 / 180
» System-Level Design for FPGAs
Sort
View
DATE
2010
IEEE
174views Hardware» more  DATE 2010»
15 years 9 months ago
VAPRES: A Virtual Architecture for Partially Reconfigurable Embedded Systems
- Due to the runtime flexibility offered by field programmable gate arrays (FPGAs), FPGAs are popular devices for stream processing systems, since many stream processing applicatio...
Abelardo Jara-Berrocal, Ann Gordon-Ross
TRETS
2010
142views more  TRETS 2010»
15 years 2 months ago
Performance Analysis Framework for High-Level Language Applications in Reconfigurable Computing
s, and abstractions, typically enabling faster development times than with traditional Hardware ion Languages (HDLs). However, programming at a higher level of abstraction is typic...
John Curreri, Seth Koehler, Alan D. George, Brian ...
ICCD
2005
IEEE
246views Hardware» more  ICCD 2005»
16 years 1 months ago
H-SIMD Machine: Configurable Parallel Computing for Matrix Multiplication
FPGAs (Field-Programmable Gate Arrays) are often used as coprocessors to boost the performance of dataintensive applications [1, 2]. However, mapping algorithms onto multimillion-...
Xizhen Xu, Sotirios G. Ziavras
ICCAD
2007
IEEE
157views Hardware» more  ICCAD 2007»
16 years 1 months ago
Performance and power evaluation of a 3D CMOS/nanomaterial reconfigurable architecture
—In this paper, we introduce a novel reconfigurable architecture, named 3D nFPGA, which utilizes 3D integration techniques and new nanoscale materials synergistically. The propos...
Chen Dong, Deming Chen, Sansiri Tanachutiwat, Wei ...
SLIP
2005
ACM
15 years 10 months ago
A 3-D FPGA wire resource prediction model validated using a 3-D placement and routing tool
The interconnection architecture of FPGAs such as switches dominates performance of FPGAs. Three-dimensional integration of FPGAs overcomes interconnect limitations by allowing in...
Young-Su Kwon, Payam Lajevardi, Anantha P. Chandra...