897 search results - page 82 / 180 » System-Level Design for FPGAs |
136
click to vote
ISSS
1998
IEEE
15 years 8 months ago
1998
IEEE
In this paper, we propose the target board architecture of a rapid prototyping embedded system based on hardware software codesign. The target board contains a TMS320C30 DSP proce...
122
click to vote
FPL
1997
Springer
15 years 8 months ago
1997
Springer
Abstract. Pipeline morphing is a simple but e ective technique for recon guring pipelined FPGA designs at run time. By overlapping computation and recon guration, the latency assoc...
119
click to vote
EURODAC
1994
IEEE
15 years 8 months ago
1994
IEEE
We consider a switch module routing problem for symmetric array FPGAs. The work is motivated by two applications. The rst is that of eciently evaluating switch module designs [8]...
141
click to vote
ICCD
1994
IEEE
15 years 8 months ago
1994
IEEE
There is currently great interest in using fixed arrays of FPGAs for logic emulators, custom computing devices, and software accelerators. An important part of designing such a sy...
162
click to vote
FPL
2009
Springer
15 years 8 months ago
2009
Springer
High-Level Synthesis (HLS) is the field of transforming a high-level programming language, such as C, into a register transfer level(RTL) description of the design. In HLS, Binary...