897 search results - page 90 / 180 » System-Level Design for FPGAs |
126
Voted
ISORC
2008
IEEE
15 years 11 months ago
2008
IEEE
The specific constraints that must be satisfied by embedded systems, such as timeliness, energy efficiency of battery-operated devices, dependable operation in safety-relevant sce...
117
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MEMOCODE
2007
IEEE
15 years 10 months ago
2007
IEEE
This design presents a system optimized for complex matrix multiplications on the XUP Virtex-II board. Utilizing the GEZEL HW/SW co-simulation environment, the resulting system ac...
119
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DAC
1997
ACM
15 years 8 months ago
1997
ACM
This paper presents a power evaluation framework designed for estimating power consumption of a new video telephone compression standard, ITU-H.263, at the system level. A hierarc...
141
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DSD
2009
IEEE
15 years 11 months ago
2009
IEEE
Multicore and manycore processors are the new wave of computing, offering high performance by using large numbers of simple processors. In this paper, we describe the implementati...
123
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DSD
2005
IEEE
15 years 10 months ago
2005
IEEE
This paper first defines the n-input q-output WS function, as a mathematical model of the combinational part of the distributed arithmetic of a finite impulse response (FIR) ...