897 search results - page 95 / 180 » System-Level Design for FPGAs |
132
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FPL
2006
Springer
15 years 8 months ago
2006
Springer
This paper is concerned with the application of formal optimisation methods to the design of mixed-granularity FPGAs. In particular, we investigate the appropriate mix and floorpl...
170
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CONIELECOMP
2011
IEEE
14 years 8 months ago
2011
IEEE
This work focuses on developing systems of blocks in SIMULINK and VHDL to reuse on design of applications involving the recognition of polygonal objects. Usage of this work reduce...
150
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ICCAD
2007
IEEE
16 years 1 months ago
2007
IEEE
— Small gates, such as AND2, XOR2 and MUX2, have been mixed with lookup tables (LUTs) inside the programmable logic block (PLB) to reduce area and power and increase performance ...
150
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DAC
2004
ACM
15 years 10 months ago
2004
ACM
Silicon compilers are often used in conjunction with Field Programmable Gate Arrays (FPGAs) to deliver flexibility, fast prototyping, and accelerated time-to-market. Many of these...
137
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FPGA
2001
ACM
15 years 9 months ago
2001
ACM
Conventional technology mapping algorithms for SRAM-based Field Programmable Gate Arrays (FPGAs) are normally carried out on a fixed logic decomposition of a circuit. The impact o...