897 search results - page 97 / 180 » System-Level Design for FPGAs |
146
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APCCAS
2006
IEEE
15 years 6 months ago
2006
IEEE
Abstract-- Multi-context FPGAs (MC-FPGAs) have multiple memory bits per configuration bit forming configuration planes for fast switching between contexts. The additional memory pl...
122
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DATE
2005
IEEE
15 years 10 months ago
2005
IEEE
attributed to the high regularity of memories, PAs and FPGAs, and the ease with which they can be tested and reconfigured to avoid faulty elements. Digital microfluidicsbased bioch...
159
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CODES
2006
IEEE
15 years 10 months ago
2006
IEEE
Process variability has a detrimental impact on the performance of memories and other system components, which can lead to parametric yield loss at the system level due to timing ...
109
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DAC
2002
ACM
16 years 5 months ago
2002
ACM
A regular circuit structure called a River PLA and its reconfigurable version, Glacier PLA, are presented. River PLAs provide greater regularity than circuits implemented with sta...
118
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DAC
2004
ACM
16 years 5 months ago
2004
ACM
This paper shows a method to decompose a given multipleoutput circuit into two circuits with intermediate outputs. We use a BDD for characteristic function (BDD for CF) to represe...