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ISCA
2005
IEEE
128views Hardware» more  ISCA 2005»
15 years 3 months ago
An Evaluation Framework and Instruction Set Architecture for Ion-Trap Based Quantum Micro-Architectures
: The theoretical study of quantum computation has yielded efficient algorithms for some traditionally hard problems. Correspondingly, experimental work on the underlying physical...
Steven Balensiefer, Lucas Kreger-Stickles, Mark Os...
ISSS
1996
IEEE
129views Hardware» more  ISSS 1996»
15 years 1 months ago
Hardware/Software Partitioning with Iterative Improvement Heuristics
The paper presents two heuristics for hardware/software partitioning of system level specifications. The main objective is to achieve performance optimization with a limited hardw...
Petru Eles, Zebo Peng, Krzysztof Kuchcinski, Alex ...
SIGMETRICS
2005
ACM
110views Hardware» more  SIGMETRICS 2005»
15 years 3 months ago
Empirical evaluation of multi-level buffer cache collaboration for storage systems
To bridge the increasing processor-disk performance gap, buffer caches are used in both storage clients (e.g. database systems) and storage servers to reduce the number of slow di...
Zhifeng Chen, Yan Zhang, Yuanyuan Zhou, Heidi Scot...
ERSA
2006
124views Hardware» more  ERSA 2006»
14 years 11 months ago
RTOS-Based Hardware Software Communications and Configuration Management in the Context of a Smart Camera
This paper deals with the question of task communication and configuration dynamic management in the context of hardware and software implementations. Our approach is based on a c...
Yvan Eustache, Jean-Philippe Diguet, Milad El Khod...
VLSID
2008
IEEE
128views VLSI» more  VLSID 2008»
15 years 10 months ago
Addressing the Challenges of Synchronization/Communication and Debugging Support in Hardware/Software Cosimulation
With increasing adoption of Electronic System Level (ESL) tools, effective design and validation time has reduced to a considerable extent. Cosimulation is found to be a principal...
Banit Agrawal, Timothy Sherwood, Chulho Shin, Simo...