Sciweavers

217 search results - page 14 / 44
» System-Level Modeling and Verification: a Comprehensive Desi...
Sort
View
62
Voted
DATE
2005
IEEE
155views Hardware» more  DATE 2005»
15 years 3 months ago
RTK-Spec TRON: A Simulation Model of an ITRON Based RTOS Kernel in SystemC
This paper presents the methodology and the modeling constructs we have developed to capture the real time aspects of RTOS simulation models in a System Level Design Language (SLD...
M. Abdelsalam Hassan, Keishi Sakanushi, Yoshinori ...
FMSD
2002
107views more  FMSD 2002»
14 years 9 months ago
Verification of Out-Of-Order Processor Designs Using Model Checking and a Light-Weight Completion Function
We present a new technique for verification of complex hardware devices that allows both generality andahighdegreeofautomation.Thetechniqueisbasedonournewwayofconstructinga"li...
Sergey Berezin, Edmund M. Clarke, Armin Biere, Yun...
DATE
2003
IEEE
134views Hardware» more  DATE 2003»
15 years 2 months ago
A Multi-Level Design Flow for Incorporating IP Cores: Case Study of 1D Wavelet IP Integration
The design of high performance multimedia systems in a short time force us to use IP's blocks in many designs. However, their correct integration in a design implies more com...
Adel Baganne, Imed Bennour, Mehrez Elmarzougui, Ri...
101
Voted
DT
2006
180views more  DT 2006»
14 years 9 months ago
A SystemC Refinement Methodology for Embedded Software
process: Designers must define higher abstraction levels that allow system modeling. They must use description languages that handle both hardware and software components to descri...
Jérôme Chevalier, Maxime de Nanclas, ...
FDL
2007
IEEE
15 years 1 months ago
Towards Assertion Based Verification of Analog and Mixed Signal Designs Using PSL
Abstract-- Analog and Mixed Signal (AMS) designs are important integrated systems that link digital circuits to the analog world. Following the success of PSL verification methodol...
Ghiath Al Sammane, Mohamed H. Zaki, Zhi Jie Dong, ...