217 search results - page 16 / 44 » System-Level Modeling and Verification: a Comprehensive Desi... |
ECBS
2006
IEEE
15 years 4 months ago
2006
IEEE
We present in this paper a unified paradigm for the verification and validation of software and systems engineering design models expressed in UML 2.0 or SysML. This paradigm reli...
97
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DAC
2002
ACM
16 years 1 months ago
2002
ACM
The ForSyDe methodology has been developed for system level design. In this paper we present formal transformation methods for the refinement of an abstract and formal system mode...
106
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CORR
2010
Springer
15 years 14 days ago
2010
Springer
Reusable software components need well-defined interfaces, rigorously and completely documented features, and a design amenable both to reuse and to formal verification; all these...
119
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VLSID
2000
IEEE
15 years 3 months ago
2000
IEEE
We address the problem of verifying the correctness of pre-silicon models of a microprocessor. We touch on the latest advances in this area by considering two different aspects of...
111
Voted
ACMICEC
2005
ACM
15 years 6 months ago
2005
ACM
Current composite web service development and management solutions, e.g. BPEL, do not cater for assessing and maintaining comparability of business partners during business collab...