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95
Voted
ISSS
2002
IEEE
125views Hardware» more  ISSS 2002»
15 years 5 months ago
Design Experience of a Chip Multiprocessor Merlot and Expectation to Functional Verification
We have fabricated a Chip Multiprocessor prototype code-named Merlot to proof our novel speculative multithreading architecture. On Merlot, multiple threads provide wider issue wi...
Satoshi Matsushita
AAAI
2000
15 years 1 months ago
The Systems Engineering Process Activities (SEPA) Methodology and Tool Suite
or cone, abstraction is chosen to represent a spectrum of user inputs/requirements that are narrowed, refined, and structured into a system design. User inputs require refinement f...
K. Suzanne Barber, Thomas J. Graser, Paul Grisham,...
116
Voted
DAC
1999
ACM
15 years 4 months ago
Behavioral Synthesis of Analog Systems Using Two-layered Design Space Exploration
This paper presents a novel approach for synthesis of analog systems from behavioral VHDL-AMS specifications. We implemented this approach in the VASE behavioral-synthesis tool. ...
Alex Doboli, Adrián Núñez-Ald...
118
Voted
DALT
2004
Springer
15 years 4 months ago
Modeling and Verification of Distributed Autonomous Agents Using Logic Programming
Systems of autonomous agents providing automated services over the Web are fast becoming a reality. Often these agent systems are constructed using procedural architectures that pr...
L. Robert Pokorny, C. R. Ramakrishnan
DAC
2008
ACM
16 years 1 months ago
Specify-explore-refine (SER): from specification to implementation
Driven by increasing complexity and reliability demands, the Japanese Aerospace Exploration Agency (JAXA) in 2004 commissioned development of ELEGANT, a complete SpecC-based envir...
Andreas Gerstlauer, Junyu Peng, Dongwan Shin, Dani...