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» System-Level Modeling and Verification: a Comprehensive Desi...
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ASPDAC
2006
ACM
109views Hardware» more  ASPDAC 2006»
15 years 6 months ago
Cycle error correction in asynchronous clock modeling for cycle-based simulation
— As the complexity of SoCs is increasing, hardware/software co-verification becomes an important part of system verification. C-level cycle-based simulation could be an efficien...
Junghee Lee, Joonhwan Yi
107
Voted
SIGSOFT
2007
ACM
16 years 1 months ago
A behavioural model for product families
In this paper we propose a behavioural model, namely the Extended Modal Labeled Transition Systems, as a basis for the formalization of the different notions of variability usuall...
Alessandro Fantechi, Stefania Gnesi
ASPDAC
2009
ACM
249views Hardware» more  ASPDAC 2009»
15 years 5 months ago
Automatic generation of Cycle Accurate and Cycle Count Accurate transaction level bus models from a formal model
— This paper proposes the first automatic approach to simultaneously generate Cycle Accurate and Cycle Count Accurate transaction level bus models. Since TLM (Transaction Level M...
Chen Kang Lo, Ren-Song Tsay
117
Voted
MEMOCODE
2010
IEEE
14 years 10 months ago
Proving transaction and system-level properties of untimed SystemC TLM designs
Electronic System Level (ESL) design manages the complexity of todays systems by using abstract models. In this context Transaction Level Modeling (TLM) is state-of-theart for desc...
Daniel Große, Hoang M. Le, Rolf Drechsler
ASWEC
2007
IEEE
15 years 6 months ago
A Formal Model of Service-Oriented Design Structure
—Service-Oriented Computing (SOC) is an emerging paradigm for developing software systems that employ services. Presently there is already much research effort in the areas of se...
Mikhail Perepletchikov, Caspar Ryan, Keith Frampto...