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» System-Level Modeling and Verification: a Comprehensive Desi...
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HF
2002
95views more  HF 2002»
15 years 5 days ago
Formal Verification of Human-Automation Interaction
This paper discusses a formal and rigorous approach to the analysis of operator interaction with machines. It addresses the acute problem of detecting design errors in human-machi...
Asaf Degani, Michael Heymann
116
Voted
ECBS
2007
IEEE
145views Hardware» more  ECBS 2007»
15 years 4 months ago
Automatic Verification and Performance Analysis of Time-Constrained SysML Activity Diagrams
We present in this paper a new approach for the automatic verification and performance analysis of SysML activity diagrams. Since timeliness is important in the design and analysi...
Yosr Jarraya, Andrei Soeanu, Mourad Debbabi, Fawzi...
ICCAD
1999
IEEE
81views Hardware» more  ICCAD 1999»
15 years 4 months ago
Modeling design constraints and biasing in simulation using BDDs
Constraining and input biasing are frequently used techniques in functional verification methodologies based on randomized simulation generation. Constraints confine the simulatio...
Jun Yuan, Kurt Shultz, Carl Pixley, Hillel Miller,...
ICSM
2008
IEEE
15 years 6 months ago
Supporting requirements reuse in multi-agent system product line design and evolution
A principal goal of agent-oriented software engineering (AOSE) is to provide the mechanisms for reusing, maintaining and allowing the evolution of agent-based software systems. Ou...
Josh Dehlinger, Robyn R. Lutz
MTV
2005
IEEE
128views Hardware» more  MTV 2005»
15 years 6 months ago
Automated Extraction of Structural Information from SystemC-based IP for Validation
The increasing complexity and size of system level design models introduces a difficult challenge for validating them. Hence, in most industries, design validation takes a large p...
David Berner, Hiren D. Patel, Deepak Mathaikutty, ...