217 search results - page 29 / 44 » System-Level Modeling and Verification: a Comprehensive Desi... |
BCSHCI
2007
15 years 1 months ago
2007
The use of formal models for user interface design can provide a number of benefits. It can help to ensure consistency across designs for multiple platforms, prove properties such...
102
Voted
DATE
2003
IEEE
15 years 5 months ago
2003
IEEE
This paper presents VISTA, a new methodology and tool dedicated to analyse system level performance by executing full-scale SW application code on a transaction-level model of the...
111
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ATAL
2009
Springer
15 years 7 months ago
2009
Springer
The agentTool III (aT3 ) development environment is built on the Eclipse platform and provides traditional model creation tools to support the analysis, design, and implementation...
136
Voted
DATE
2009
IEEE
15 years 3 months ago
2009
IEEE
—Power management at any abstraction level is a key issue for many mobile multimedia and embedded applications. In this paper a design workflow to generate system-level power mo...
89
Voted
DAC
2004
ACM
16 years 1 months ago
2004
ACM
The increasing complexity of today's mixed-signal integrated circuits necessitates both top-down and bottom-up system-level verification. Time-domain state-space modeling and...