Sciweavers

217 search results - page 36 / 44
» System-Level Modeling and Verification: a Comprehensive Desi...
Sort
View
ICS
2005
Tsinghua U.
15 years 3 months ago
Improved automatic testcase synthesis for performance model validation
Performance simulation tools must be validated during the design process as functional models and early hardware are developed, so that designers can be sure of the performance of...
Robert H. Bell Jr., Lizy Kurian John
RTCSA
2008
IEEE
15 years 3 months ago
Real-Time Communications Over Cluster-Tree Sensor Networks with Mobile Sink Behaviour
· Modelling the fundamental performance limits of Wireless Sensor Networks (WSNs) is of paramount importance to understand the behaviour of WSN under worst-case conditions and to...
Petr Jurcík, Ricardo Severino, Anis Koubaa,...
WSC
1997
14 years 11 months ago
Applications of the Universal Joint Task List to Joint Exercise Results
The foundation of readiness is training. The Chairman, Joint Chiefs of Staff (CJCS) Joint Training Program institutes methods for identifying training requirements through review ...
Sam H. Parry, Michael C. McAneny, Richard J. Drome...
77
Voted
DATE
2006
IEEE
108views Hardware» more  DATE 2006»
15 years 3 months ago
Software-friendly HW/SW co-simulation: an industrial case study
This paper proposes a novel HW/SW co-simulation approach that minimizes the impact on software designers. We propose a SystemC-based system that enables the software team to test ...
Juanjo Noguera, Luis Baldez, Narcis Simon, Lluis A...
ICCAD
2009
IEEE
121views Hardware» more  ICCAD 2009»
14 years 7 months ago
MOLES: Malicious off-chip leakage enabled by side-channels
Economic incentives have driven the semiconductor industry to separate design from fabrication in recent years. This trend leads to potential vulnerabilities from untrusted circui...
Lang Lin, Wayne Burleson, Christof Paar