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» System-in-Package Testing: Problems and Solutions
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DAC
2009
ACM
15 years 2 months ago
Vicis: a reliable network for unreliable silicon
Process scaling has given designers billions of transistors to work with. As feature sizes near the atomic scale, extensive variation and wearout inevitably make margining unecono...
David Fick, Andrew DeOrio, Jin Hu, Valeria Bertacc...
CVPR
2008
IEEE
15 years 11 months ago
Margin-based discriminant dimensionality reduction for visual recognition
Nearest neighbour classifiers and related kernel methods often perform poorly in high dimensional problems because it is infeasible to include enough training samples to cover the...
Hakan Cevikalp, Bill Triggs, Frédéri...
SSDBM
2005
IEEE
175views Database» more  SSDBM 2005»
15 years 3 months ago
Assumption-Free Anomaly Detection in Time Series
Recent advancements in sensor technology have made it possible to collect enormous amounts of data in real time. However, because of the sheer volume of data most of it will never...
Li Wei, Nitin Kumar, Venkata Nishanth Lolla, Eamon...
DAC
2005
ACM
15 years 10 months ago
Robust gate sizing by geometric programming
We present an efficient optimization scheme for gate sizing in the presence of process variations. Using a posynomial delay model, the delay constraints are modified to incorporat...
Jaskirat Singh, Vidyasagar Nookala, Zhi-Quan Luo, ...
84
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HPCA
2009
IEEE
15 years 10 months ago
Dacota: Post-silicon validation of the memory subsystem in multi-core designs
The number of functional errors escaping design verification and being released into final silicon is growing, due to the increasing complexity and shrinking production schedules ...
Andrew DeOrio, Ilya Wagner, Valeria Bertacco