In modular testing of system-on-a-chip (SoC), test access mechanisms (TAMs) are used to transport test data between the input/output pins of the SoC and the cores under test. Prio...
We present a mathematical model for the problem of scheduling tests for core-based system-on-chip (SOC) VLSI designs. Given a set of tests for each core in the SOC and a set of te...
After thirty-plus years of making small “mid-course corrections” types of changes to the support paradigm, many on the Iowa State University campus thought it was time to make...
— – Major research challenges in the next generation of wireless networks include the provisioning of worldwide seamless mobility across heterogeneous wireless networks, the im...
Much excitement has been generated by the success of stochastic local search procedures at finding solutions to large, very hard satisfiability problems. Many of the problems on wh...