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» Systems Architectures for Transactional Network Interface
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153
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IPPS
2010
IEEE
15 years 26 days ago
Efficient hardware support for the Partitioned Global Address Space
We present a novel architecture of a communication engine for non-coherent distributed shared memory systems. The shared memory is composed by a set of nodes exporting their memory...
Holger Fröning, Heiner Litz
169
Voted
CCECE
2006
IEEE
15 years 9 months ago
QOS Driven Network-on-Chip Design for Real Time Systems
Real Time embedded system designers are facing extreme challenges in underlying architectural design selection. It involves the selection of a programmable, concurrent, heterogene...
Ankur Agarwal, Mehmet Mustafa, Abhijit S. Pandya
ICC
1997
IEEE
155views Communications» more  ICC 1997»
15 years 7 months ago
Design of Call Control Signaling in Wireless ATM Networks
: In this paper, a multiservice, local-area, wireless access ATM system is explored from a signaling protocol viewpoint. The signaling architecture considered here follows the sign...
Nikolaos H. Loukas, Nikos I. Passas, Lazaros F. Me...
124
Voted
SOSP
2005
ACM
16 years 14 days ago
THINC: a virtual display architecture for thin-client computing
Rapid improvements in network bandwidth, cost, and ubiquity combined with the security hazards and high total cost of ownership of personal computers have created a growing market...
Ricardo A. Baratto, Leonard N. Kim, Jason Nieh
NOCS
2008
IEEE
15 years 10 months ago
Debugging Distributed-Shared-Memory Communication at Multiple Granularities in Networks on Chip
We present a methodology to debug a SOC by concentrating on its communication. Our extended communication model includes a) multiple signal groups per interface protocol at each I...
Bart Vermeulen, Kees Goossens, Siddharth Umrani