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TCAD
2010
150views more  TCAD 2010»
14 years 6 months ago
Voltage and Temperature Aware Statistical Leakage Analysis Framework Using Artificial Neural Networks
Artificial neural networks (ANNs) have shown great promise in modeling circuit parameters for computer aided design applications. Leakage currents, which depend on process paramete...
Janakiraman Viraraghavan, Bharadwaj Amrutur, V. Vi...
TCAD
2010
88views more  TCAD 2010»
14 years 6 months ago
Stress Aware Layout Optimization Leveraging Active Area Dependent Mobility Enhancement
Starting from the 90nm technology node, process induced stress has played a key role in the design of highperformance devices. The emergence of source/drain silicon germanium (S/D ...
Ashutosh Chakraborty, Sean X. Shi, David Z. Pan
TCAD
2010
194views more  TCAD 2010»
14 years 6 months ago
Layout Decomposition Approaches for Double Patterning Lithography
Abstract--In double patterning lithography (DPL) layout decomposition for 45nm and below process nodes, two features must be assigned opposite colors (corresponding to different ex...
Andrew B. Kahng, Chul-Hong Park, Xu Xu, Hailong Ya...
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TCAD
2010
124views more  TCAD 2010»
14 years 6 months ago
A Reconfigurable Source-Synchronous On-Chip Network for GALS Many-Core Platforms
Abstract--This paper presents a GALS-compatible circuitswitched on-chip network that is well suited for use in many-core platforms targeting streaming DSP and embedded applications...
Anh Thien Tran, Dean Nguyen Truong, Bevan M. Baas
TCAD
2010
136views more  TCAD 2010»
14 years 6 months ago
Bounded Model Debugging
Design debugging is a major bottleneck in modern VLSI design flows as both the design size and the length of the error trace contribute to its inherent complexity. With typical des...
Brian Keng, Sean Safarpour, Andreas G. Veneris
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