Sciweavers

332 search results - page 59 / 67
» T: integrated building blocks for parallel computing
Sort
View
AICCSA
2005
IEEE
124views Hardware» more  AICCSA 2005»
15 years 4 months ago
On multicast scheduling and routing in multistage Clos networks
Multicast communication, which involves transmitting information from one node to multiple nodes, is a vital operation in both broadband integrated services digital networks (BISD...
Bin Tang
FPGA
2004
ACM
121views FPGA» more  FPGA 2004»
15 years 4 months ago
Highly pipelined asynchronous FPGAs
We present the design of a high-performance, highly pipelined asynchronous FPGA. We describe a very fine-grain pipelined logic block and routing interconnect architecture, and sh...
John Teifel, Rajit Manohar
93
Voted
DSL
1997
15 years 7 days ago
Experience with a Language for Writing Coherence Protocols
In this paper we describe our experience with Teapot [7], a domain-specific language for writing cache coherence protocols. Cache coherence is of concern when parallel and distrib...
Satish Chandra, James R. Larus, Michael Dahlin, Br...
101
Voted
DAC
1999
ACM
15 years 3 months ago
Panel: What is the Proper System on Chip Design Methodology
ion model or flexible PCB solutions cannot offer a valid solution for the next millinium SoCs . James G. Dougherty, Integrated Systems Silicon LTD, Belfast, Northern Ireland ISS an...
Richard Goering, Pierre Bricaud, James G. Doughert...
90
Voted
ICS
2004
Tsinghua U.
15 years 4 months ago
Applications of storage mapping optimization to register promotion
Storage mapping optimization is a flexible approach to folding array dimensions in numerical codes. It is designed to reduce the memory footprint after a wide spectrum of loop tr...
Patrick Carribault, Albert Cohen