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LCTRTS
2007
Springer
15 years 8 months ago
Addressing instruction fetch bottlenecks by using an instruction register file
The Instruction Register File (IRF) is an architectural extension for providing improved access to frequently occurring instructions. An optimizing compiler can exploit an IRF by ...
Stephen Roderick Hines, Gary S. Tyson, David B. Wh...
LCTRTS
2007
Springer
15 years 8 months ago
Compiler-managed partitioned data caches for low power
Set-associative caches are traditionally managed using hardwarebased lookup and replacement schemes that have high energy overheads. Ideally, the caching strategy should be tailor...
Rajiv A. Ravindran, Michael L. Chu, Scott A. Mahlk...
SEMWEB
2007
Springer
15 years 8 months ago
Extending Fuzzy Description Logics with a Possibilistic Layer
Classical ontologies are not suitable to represent imprecise nor uncertain pieces of information. As a solution we will combine fuzzy Description Logics with a possibilistic layer....
Fernando Bobillo, Miguel Delgado, Juan Góme...
UM
2007
Springer
15 years 8 months ago
The Effect of Model Granularity on Student Performance Prediction Using Bayesian Networks
A standing question in the field of Intelligent Tutoring Systems and User Modeling in general is what is the appropriate level of model granularity (how many skills to model) and h...
Zachary A. Pardos, Neil T. Heffernan, Brigham Ande...
APCSAC
2006
IEEE
15 years 8 months ago
A High Performance Simulator System for a Multiprocessor System Based on a Multi-way Cluster
In the ubiquitous era, it is necessary to research the architectures of multiprocessor system with high performance and low power consumption. A simulator developed in high level l...
Arata Shinozaki, Masatoshi Shima, Minyi Guo, Mitsu...
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