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DAC
2005
ACM
15 years 10 days ago
TCAM enabled on-chip logic minimization
This paper presents an efficient hardware architecture of an on-chip logic minimization coprocessor. The proposed architecture employs TCAM cells to provide fastest and memory eļ¬...
Seraj Ahmad, Rabi N. Mahapatra
ASAP
2004
IEEE
101views Hardware» more  ASAP 2004»
15 years 2 months ago
Register Organization for Enhanced On-Chip Parallelism
Large register file with multiple ports is a critical component of a high-performance processor. A large number of registers are necessary for processing a larger number of in-fli...
Rama Sangireddy