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ISPD
2012
ACM
288views Hardware» more  ISPD 2012»
13 years 9 months ago
Construction of realistic gate sizing benchmarks with known optimal solutions
Gate sizing in VLSI design is a widely-used method for power or area recovery subject to timing constraints. Several previous works have proposed gate sizing heuristics for power ...
Andrew B. Kahng, Seokhyeong Kang
LCTRTS
2009
Springer
15 years 8 months ago
Addressing the challenges of DBT for the ARM architecture
Dynamic binary translation (DBT) can provide security, virtualization, resource management and other desirable services to embedded systems. Although DBT has many benefits, its r...
Ryan W. Moore, José Baiocchi, Bruce R. Chil...
INFOCOM
2007
IEEE
15 years 8 months ago
Two-Tier Load Balancing in OSPF Wireless Back-Hauls
Abstract— High-speed wireless communication technology (e.g. WiMAX) makes it feasible and cost-effective to build wireless back-hauls for Internet access. Compared to wired count...
Xiaowen Zhang, Hao Zhu
CODES
2005
IEEE
15 years 7 months ago
SOMA: a tool for synthesizing and optimizing memory accesses in ASICs
Arbitrary memory dependencies and variable latency memory systems are major obstacles to the synthesis of large-scale ASIC systems in high-level synthesis. This paper presents SOM...
Girish Venkataramani, Tiberiu Chelcea, Seth Copen ...
SAS
2005
Springer
114views Formal Methods» more  SAS 2005»
15 years 7 months ago
Type-Safe Optimisation of Plugin Architectures
Programmers increasingly implement plugin architectures in type-safe object-oriented languages such as Java. A virtual machine can dynamically load class files containing plugins,...
Neal Glew, Jens Palsberg, Christian Grothoff