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ICCAD
2004
IEEE
87views Hardware» more  ICCAD 2004»
15 years 11 months ago
Exploiting level sensitive latches in wire pipelining
Wire pipelining emerges as a new necessity for global wires due to increasing wire delay, shrinking clock period and growing chip size. Existing approaches on wire pipelining are ...
V. Seth, Min Zhao, Jiang Hu
IUI
2009
ACM
15 years 10 months ago
Structuring and manipulating hand-drawn concept maps
Concept maps are an important tool to knowledge organization, representation, and sharing. Most current concept map tools do not provide full support for hand-drawn concept map cr...
Yingying Jiang, Feng Tian, XuGang Wang, Xiaolong Z...
PPPJ
2009
ACM
15 years 8 months ago
Automatic parallelization for graphics processing units
Accelerated graphics cards, or Graphics Processing Units (GPUs), have become ubiquitous in recent years. On the right kinds of problems, GPUs greatly surpass CPUs in terms of raw ...
Alan Leung, Ondrej Lhoták, Ghulam Lashari
ICS
2009
Tsinghua U.
15 years 8 months ago
Adagio: making DVS practical for complex HPC applications
Power and energy are first-order design constraints in high performance computing. Current research using dynamic voltage scaling (DVS) relies on trading increased execution time...
Barry Rountree, David K. Lowenthal, Bronis R. de S...
ICS
2009
Tsinghua U.
15 years 8 months ago
Parametric multi-level tiling of imperfectly nested loops
Tiling is a crucial loop transformation for generating high performance code on modern architectures. Efficient generation of multilevel tiled code is essential for maximizing da...
Albert Hartono, Muthu Manikandan Baskaran, C&eacut...