2956 search results - page 121 / 592 » Targeted Data Prefetching |
128
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HPCA
2005
IEEE
16 years 2 months ago
2005
IEEE
The use of large instruction windows coupled with aggressive out-oforder and prefetching capabilities has provided significant improvements in processor performance. In this paper...
181
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HPCA
2004
IEEE
16 years 2 months ago
2004
IEEE
Recent research suggests that there are large variations in a cache's spatial usage, both within and across programs. Unfortunately, conventional caches typically employ fixe...
137
Voted
MSS
2000
IEEE
15 years 7 months ago
2000
IEEE
Phoenix is a fault-tolerantreal-time network-attachedstorage device (NASD). Like other NASD architectures, Phoenix provides an object-based interface to data stored on network-att...
120
Voted
PLDI
1999
ACM
15 years 6 months ago
1999
ACM
Hardware trends have produced an increasing disparity between processor speeds and memory access times. While a variety of techniques for tolerating or reducing memory latency hav...
141
Voted
CGO
2004
IEEE
15 years 6 months ago
2004
IEEE
The effective use of processor caches is crucial to the performance of applications. It has been shown that cache misses are not evenly distributed throughout a program. In applic...