Sciweavers

314 search results - page 18 / 63
» Targeting Heterogeneous Architectures in ASSIST: Experimenta...
Sort
View
FPL
2007
Springer
124views Hardware» more  FPL 2007»
15 years 3 months ago
HARTES Toolchain Early Evaluation: Profiling, Compilation and HDL Generation
The aim of the hArtes project is to facilitate and automate the rapid design and development of heterogeneous embedded systems, targeting a combination of a general purpose embedd...
Koen Bertels, Georgi Kuzmanov, Elena Moscu Panaint...
DATE
2007
IEEE
185views Hardware» more  DATE 2007»
15 years 3 months ago
An ILP formulation for system-level application mapping on network processor architectures
Current day network processors incorporate several architectural features including symmetric multi-processing (SMP), block multi-threading, and multiple memory elements to suppor...
Christopher Ostler, Karam S. Chatha
SENSYS
2009
ACM
15 years 4 months ago
Darjeeling, a feature-rich VM for the resource poor
The programming and retasking of sensor nodes could benefit greatly from the use of a virtual machine (VM) since byte code is compact, can be loaded on demand, and interpreted on...
Niels Brouwers, Koen Langendoen, Peter Corke
MOBIHOC
2007
ACM
15 years 9 months ago
Capacity scaling in delay tolerant networks with heterogeneous mobile nodes
We provide a general framework for the analysis of the capacity scaling properties in mobile ad-hoc networks with heterogeneous nodes and spatial inhomogeneities. Existing analyti...
Michele Garetto, Paolo Giaccone, Emilio Leonardi
DATE
2004
IEEE
114views Hardware» more  DATE 2004»
15 years 1 months ago
Power Aware Variable Partitioning and Instruction Scheduling for Multiple Memory Banks
Many high-end DSP processors employ both multiple memory banks and heterogeneous register files to improve performance and power consumption. The complexity of such architectures ...
Zhong Wang, Xiaobo Sharon Hu