119 search results - page 7 / 24 » Targeting Tiled Architectures in Design Exploration |
99
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CASES
2006
ACM
15 years 3 months ago
2006
ACM
Developing an optimizing compiler for a newly proposed architecture is extremely difficult when there is only a simulator of the machine available. Designing such a compiler requ...
DATE
2009
IEEE
15 years 4 months ago
2009
IEEE
—This paper presents a tool for exploring different parallelization options for an application. It can be used to quickly find a high-quality match between an application and a ...
102
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ISLPED
2005
ACM
15 years 3 months ago
2005
ACM
This paper explores the power implications of replacing global chip wires with an on-chip network. We optimize network links by varying repeater spacing, link pipelining, and volt...
DATE
2010
IEEE
15 years 2 months ago
2010
IEEE
There is today little doubt on the fact that a high-performance and cost-effective Network-on-Chip can only be designed in 45nm and beyond under a relaxed synchronization assumpti...
GLVLSI
2000
IEEE
15 years 1 months ago
2000
IEEE
System-level power exploration requires tools for estimation of the overall power consumed by a system, as well as a detailed breakdown of the consumption of its main functional b...