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» Task Graph Scheduling Using Timed Automata
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DFT
2003
IEEE
113views VLSI» more  DFT 2003»
15 years 6 months ago
Buffer and Controller Minimisation for Time-Constrained Testing of System-On-Chip
Test scheduling and Test Access Mechanism (TAM) design are two important tasks in the development of a System-on-Chip (SOC) test solution. Previous test scheduling techniques assu...
Anders Larsson, Erik Larsson, Petru Eles, Zebo Pen...
COOPIS
2002
IEEE
15 years 6 months ago
An Adaptive Scheduling Service for Real-Time CORBA
CORBA is an important standard middleware used in the development of distributed applications. It has also been used with distributed real-time applications, through its extension ...
Alexandre Cervieri, Rômulo Silva de Oliveira...
ECRTS
2004
IEEE
15 years 5 months ago
A Variable Rate Execution Model
We present a task model for adaptive real-time tasks in which a task's execution rate requirements are allowed to change at any time. The model, variable rate execution (VRE)...
Steve Goddard, Xin Liu
EMSOFT
2010
Springer
14 years 11 months ago
Energy-aware packet and task co-scheduling for embedded systems
A crucial objective in battery operated embedded systems is to work under the minimal power consumption that provides a desired level of performance. Dynamic Voltage Scaling (DVS)...
Luca Santinelli, Mauro Marinoni, Francesco Prosper...
DAC
1995
ACM
15 years 5 months ago
Rephasing: A Transformation Technique for the Manipulation of Timing Constraints
- We introduce a transformation, named rephasing, that manipulates the timing parameters in control-dataflow graphs. Traditionally high-level synthesis systems for DSP have either ...
Miodrag Potkonjak, Mani B. Srivastava