10 search results - page 1 / 2 » Teaching IP Core Development: An Example |
80
Voted
MSE
2003
IEEE
15 years 2 months ago
2003
IEEE
The increasing gap between design productivity and chip complexity, and emerging systems-on-a-chip (SoC) have led to the wide utilization of reusable intellectual property (IP) co...
MSE
2005
IEEE
15 years 3 months ago
2005
IEEE
The reusing of Intellectual Property cores has been an alternative to the increasing gap between design productivity and chip complexity of emerging System-on-chip (SoC) designs. ...
91
Voted
VLSISP
2011
14 years 4 months ago
2011
This paper presents accurate area, time, power estimation models for implementations using FPGAs from the Xilinx Virtex-2Pro family [1]. These models are designed to facilitate ef...
ICASSP
2008
IEEE
15 years 3 months ago
2008
IEEE
This paper presents accurate area and power estimation models for implementations using FPGAs from the Xilinx Virtex-2Pro family. These models are designed to facilitate efficien...
ISQED
2005
IEEE
15 years 3 months ago
2005
IEEE
Today's System-on-a-Chip (SoC) design methodology provides an efficient way to develop highly integrated systems on a single chip by utilizing pre-designed intellectual prope...