21 search results - page 3 / 5 » Teaching circuits to new generations of engineers |
VLSI
2007
Springer
14 years 11 days ago
2007
Springer
— Software simulation remains the most used method for VHDL RTL functional verification. The functional verification process essentially consists of two parts. The first one is t...
DAC
1994
ACM
13 years 10 months ago
1994
ACM
A powerful combinational path sensitization engine is required for the efficient implementation of tools for test pattern generation, timing analysis, and delay fault testing. Path...
ICCAD
2008
IEEE
14 years 3 months ago
2008
IEEE
— To ensure security and robustness of the next generation of Physically Unclonable Functions (PUFs), we have developed a new methodology for PUF design. Our approach employs int...
TCAD
2008
13 years 6 months ago
2008
Starting at the 65-nm node, stress engineering to improve the performance of transistors has been a major industry focus. An intrinsic stress source--shallow trench isolation (STI)...
TCAD
2008
13 years 6 months ago
2008
BDDs have proven to be an efficient means to represent and manipulate Boolean formulae [1] and sets [2] due to their compactness and canonicality. In this work, we leverage the eff...