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ASPDAC
2008
ACM
95views Hardware» more  ASPDAC 2008»
14 years 12 months ago
MeshWorks: An efficient framework for planning, synthesis and optimization of clock mesh networks
A leaf-level clock mesh is known to be very tolerant to variations [1]. However, its use is limited to a few high-end designs because of the high power/resource requirements and la...
Anand Rajaram, David Z. Pan
DATE
2002
IEEE
115views Hardware» more  DATE 2002»
15 years 2 months ago
Design Technology for Networked Reconfigurable FPGA Platforms
Future networked appliances should be able to download new services or upgrades from the network and execute them locally. This flexibility is typically achieved by processors tha...
Steve Guccione, Diederik Verkest, Ivo Bolsens
CHARME
2001
Springer
92views Hardware» more  CHARME 2001»
15 years 1 months ago
Induction-Oriented Formal Verification in Symmetric Interconnection Networks
The framework of this paper is the formal specification and proof of applications distributed on symmetric interconnection networks, e.g. the torus or the hypercube. The algorithms...
Eric Gascard, Laurence Pierre
ASPDAC
2005
ACM
90views Hardware» more  ASPDAC 2005»
14 years 12 months ago
Feasibility analysis of messages for on-chip networks using wormhole routing
—The feasibility of a message in a network concerns if its timing property can be satisfied without jeopardizing any messages already in the network to meet their timing propert...
Zhonghai Lu, Axel Jantsch, Ingo Sander
NIPS
2004
14 years 11 months ago
Edge of Chaos Computation in Mixed-Mode VLSI - A Hard Liquid
Computation without stable states is a computing paradigm different from Turing's and has been demonstrated for various types of simulated neural networks. This publication t...
Felix Schürmann, Karlheinz Meier, Johannes Sc...