We present a fast and efficient combinatorial algorithm to simultaneously identify the candidate locations as well as the sizes of the buffers driving a clock mesh. Due to the hi...
The effectiveness of the memory hierarchy is critical for the performance of current processors. The performance of the memory hierarchy can be improved by means of program transf...
This paper presents provable work-optimal parallelizations of STL (Standard Template Library) algorithms based on the workstealing technique. Unlike previous approaches where a deq...
This paper extends the set of problems for which a global solution can be found using modern optimization methods. In particular, the method is applied to estimation of the essent...
— As across-chip wire delays exceed a clock cycle, interconnect pipelining becomes essential. However, the arbitrary insertion of flip-flops can change the differentials of lat...