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CODES
2008
IEEE
15 years 7 months ago
Static analysis for fast and accurate design space exploration of caches
Application-specific system-on-chip platforms create the opportunity to customize the cache configuration for optimal performance with minimal chip estate. Simulation, in partic...
Yun Liang, Tulika Mitra
CODES
2007
IEEE
15 years 6 months ago
Reliable multiprocessor system-on-chip synthesis
This article presents a multiprocessor system-on-chip synthesis (MPSoC) algorithm that optimizes system mean time to failure. Given a set of directed acyclic periodic graphs of co...
Changyun Zhu, Zhenyu (Peter) Gu, Robert P. Dick, L...
120
Voted
CODES
2007
IEEE
15 years 6 months ago
Three-dimensional multiprocessor system-on-chip thermal optimization
3D stacked wafer integration has the potential to improve multiprocessor system-on-chip (MPSoC) integration density, performance, and power efficiency. However, the power density...
Chong Sun, Li Shang, Robert P. Dick
LCTRTS
2007
Springer
15 years 6 months ago
Compiler-managed partitioned data caches for low power
Set-associative caches are traditionally managed using hardwarebased lookup and replacement schemes that have high energy overheads. Ideally, the caching strategy should be tailor...
Rajiv A. Ravindran, Michael L. Chu, Scott A. Mahlk...
UIST
2006
ACM
15 years 6 months ago
Multi-user, multi-display interaction with a single-user, single-display geospatial application
In this paper, we discuss our adaptation of a single-display, single-user commercial application for use in a multi-device, multi-user environment. We wrap Google Earth, a popular...
Clifton Forlines, Alan Esenther, Chia Shen, Daniel...