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ICCAD
2003
IEEE
129views Hardware» more  ICCAD 2003»
15 years 10 months ago
Performance Optimization of Latency Insensitive Systems Through Buffer Queue Sizing of Communication Channels
This paper proposes for latency insensitive systems a performance optimization technique called channel buffer queue sizing, which is performed after relay station insertion in th...
Ruibing Lu, Cheng-Kok Koh
HPCC
2009
Springer
15 years 9 months ago
On the Performance of Commit-Time-Locking Based Software Transactional Memory
Compared with lock-based synchronization techniques, Software Transactional Memory (STM) can significantly improve the programmability of multithreaded applications. Existing res...
Zhengyu He, Bo Hong
HPCA
1998
IEEE
15 years 9 months ago
Performance Study of a Concurrent Multithreaded Processor
The performance of a concurrent multithreaded architectural model, called superthreading 15 , is studied in this paper. It tries to integrate optimizing compilation techniques and...
Jenn-Yuan Tsai, Zhenzhen Jiang, Eric Ness, Pen-Chu...
ICPP
2005
IEEE
15 years 10 months ago
Incremental Parallelization Using Navigational Programming: A Case Study
We show how a series of transformations can be applied to a sequential program to obtain programs that represent successive steps in exploiting parallelism in the original algorit...
Lei Pan, Wenhui Zhang, Arthur Asuncion, Ming Kin L...
WETICE
2009
IEEE
15 years 12 months ago
PerfCloud: GRID Services for Performance-Oriented Development of Cloud Computing Applications
—Cloud Computing, born in the e-business context, and GRID computing, originated in the e-science context, are two different but similar paradigms for managing large sets of dist...
Emilio Pasquale Mancini, Massimiliano Rak, Umberto...