138 search results - page 28 / 28 » Technology Mapping for Electrically Programmable Gate Arrays |
EH
1999
IEEE
13 years 10 months ago
1999
IEEE
-- This paper describes the operation of a field programmable gate array (FPGA), the basics of current mode logic, and examines the idea of creating a SiGe heterojunction bipolar (...
FCCM
2005
IEEE
14 years 18 hour ago
2005
IEEE
Just-in-time (JIT) compilation has been used in many applications to enable standard software binaries to execute on different underlying processor architectures. We previously in...
FPGA
2010
ACM
14 years 3 months ago
2010
ACM
Guarded evaluation is a power reduction technique that involves identifying sub-circuits (within a larger circuit) whose inputs can be held constant (guarded) at specific times d...