83 search results - page 6 / 17 » Technology Mapping for Reliability Enhancement in Logic Synt... |
DAC
2008
ACM
15 years 10 months ago
2008
ACM
As integrated circuit technology plumbs ever greater depths in the scaling of feature sizes, maintaining the paradigm of deterministic Boolean computation is increasingly challeng...
GLVLSI
2009
IEEE
15 years 1 months ago
2009
IEEE
Recent technology mappers for LUT based FPGAs employ cut enumeration. Although many cuts are often needed to nd good network, enumerating all cuts with large size consumes run-tim...
GLVLSI
2010
IEEE
15 years 2 months ago
2010
IEEE
Researchers are looking for alternatives to overcome the upcoming limits of conventional hardware technologies. Reversible logic thereby established itself as a promising directio...
DATE
2010
IEEE
15 years 2 months ago
2010
IEEE
— This paper introduces the concept of kl-feasible cuts, by controlling both the number k of inputs and the number l of outputs in a circuit cut. To provide scalability, the conc...
DATE
2006
IEEE
15 years 3 months ago
2006
IEEE
We propose a logic synthesis flow which utilizes the functionality of circuit to synthesize a domino-cell network which will have more wires crosstalk-immune to each other. For t...